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INTEGRATED CIRCUITS
DATA SHEET
TDA8758 YC 8-bit low-power analog-to-digital video interface
Product specification Supersedes data of 1995 Mar 22 File under Integrated Circuits, IC02 1996 Feb 01
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
FEATURES * Two 8-bit ADCs: - one Luminance or CVBS channel - one Chrominance channel * Sampling rate up to 32 MHz * Binary or two's complement 3-state TTL outputs for each channel * Internal reference voltage regulator * TTL-compatible digital inputs and outputs * Power dissipation of 530 mW (typical) * Input selector circuit (five selectable video inputs for CVBS or YC processing) * Peak white enable input * Clamp and Automatic Gain Control (AGC) functions for Y/CVBS channel (clamping on code 64 and Peak White level control at code 255) * Clamp function for C channel (code 128) * No sample-and-hold circuit required. QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO ICCA ICCD ICCO ILE DLE EB fclk(max) B ct Ptot PARAMETER analog supply voltage digital supply voltage output stages supply voltage analog supply current digital supply current output supply current DC integral linearity error DC differential linearity error effective bits (from video input to digital outputs) maximum clock frequency maximum -3 dB bandwidth (input preamplifier) crosstalk between Y and C channels and each video input total power dissipation full-scale; 0 dB gain fclk = 32 MHz; fi = 4.43 MHz CL = 15 pF CONDITIONS MIN. 4.75 4.75 4.75 - - - - - - 30 - - - TYP. 5.0 5.0 5.0 59 28 19 0.75 0.4 7.1 32 15 -63 530 APPLICATIONS * Video signal decoding * Digital picture processing * Frame grabbing
TDA8758
* Multimedia with the Philips Desktop Video chip set (and especially SAA7196 multistandard decoder and scaler). GENERAL DESCRIPTION The TDA8758 is an 8-bit video high-speed low-power analog-to-digital conversion (ADC) interface for YC and CVBS signal processing. It converts 1-of-3 CVBS input signals or 1-of-2 YC input signals into binary or two's complement words at a sampling rate of 32 MHz. All analog signal inputs are digitally clamped and an ADC interface is provided on the Y/CVBS channel. A fast precharge on clamp and AGC is provided for start-up. All digital inputs and outputs are TTL compatible.
MAX. 5.25 5.25 5.25 70 40 28 1.5 1.0 - - - -55 724
UNIT V V V mA mA mA LSB LSB bits MHz MHz dB mW
ORDERING INFORMATION TYPE NUMBER TDA8758G 1996 Feb 01 PACKAGE NAME LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm 2 VERSION SOT313-2
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
BLOCK DIAGRAM
TDA8758
handbook, full pagewidth
V CCA SEL2 VCCA VCCD VCCO2 CCLPC 32 ANOUTC 48 45 8 44 17 1 46 15 DEC2 REG1 REG2 SDN DEC3 DEC1
V CCO1
5 2 4
10
21
41
CHROM2 CHROM1
CLAMP LEVEL 128
ADC
TTL
33 to 40 47 42
8
C7 to C0
COMPARATOR
OFC
CVBS3
6
TDA8758
INPUT SELECTOR TIMING GENERATOR
CLK
COMPARATORS Y2/CVBS2 Y1/CVBS1 9 11 AGC & CLAMP 64 ADC TTL
22 23 to 30 8
OFY
Y7 to Y0
12 SEL1
14
19 GATE A
20 C CLPY
7
13 CAGC
16
31
43
18
3
MGB469 - 1
PWE
GATE B
DGND OGND2 ANOUTY OGND1 AGND
Fig.1 Block diagram.
1996 Feb 01
3
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
PINNING SYMBOL DEC1 CHROM2 AGND CHROM1 SEL2 CVBS3 CCLPY SDN Y2/CVBS2 VCCA Y1/CVBS1 SEL1 CAGC PWE DEC3 ANOUTY REG2 DGND GATE A GATE B VCCD OFY Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 OGND2 VCCO2 C7 C6 C5 C4 C3 C2 C1 C0 1996 Feb 01 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 decoupling input 1 chrominance analog voltage input 2 analog ground chrominance analog voltage input 1 selection control input 2 luminance analog voltage input 3 Y channel clamping capacitor stabilizer decoupling node luminance analog voltage input 2 analog supply voltage (+5 V) luminance analog voltage input 1 selection control input 1 AGC capacitor peak white enable input (active LOW) decoupling input 3 analog output for Y channel decoupling input 2 (internal stabilization loop decoupling) digital ground AGC control input clamp control input digital supply voltage (+5 V) Y channel output format/chip enable (3-state input) Y channel data output; bit 7 (MSB) Y channel data output; bit 6 Y channel data output; bit 5 Y channel data output; bit 4 Y channel data output; bit 3 Y channel data output; bit 2 Y channel data output; bit 1 Y channel data output; bit 0 (LSB) output ground 2 output supply voltage 2 (+5 V) C channel data output; bit 7 (MSB) C channel data output; bit 6 C channel data output; bit 5 C channel data output; bit 4 C channel data output; bit 3 C channel data output; bit 2 C channel data output; bit 1 C channel data output; bit 0 (LSB) 4 DESCRIPTION
TDA8758
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
SYMBOL VCCO1 CLK OGND1 REG1 ANOUTC DEC2 OFC CCLPC PIN 41 42 43 44 45 46 47 48 clock input output ground 1 decoupling input 1 (internal stabilization loop decoupling) analog output for C channel decoupling input 2 C channel output format/chip enable (3-state input) C channel clamping capacitor DESCRIPTION output supply voltage 1 (+5 V)
TDA8758
45 ANOUTC
43 OGND1
48 CCLPC
40 C0
39 C1
38 C2
pin 1 index corner DEC1 CHROM2 AGND CHROM1 SEL2 CVBS3 C CLPY SDN Y2/CVBS2 1 2 3 4 5 6 7 8 9
37 C3
handbook, full pagewidth
41 VCCO1
44 REG1
46 DEC2
47 OFC
42 CLK
36 C4 35 C5 34 C6 33 C7 32 VCCO2
TDA8758
31 OGND2 30 Y0 29 Y1 28 Y2 27 Y3 26 Y4 25 Y5
V CCA 10 Y1/CVBS1 11 SEL1 12
VCCD 21
C AGC 13
PWE 14
DEC3 15
ANOUTY 16
REG2 17
DGND 18
GATE A 19
GATE B 20
OFY 22
Y6 24
Y7 23
MGB470
Fig.2 Pin configuration.
1996 Feb 01
5
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
FUNCTIONAL DESCRIPTION The TDA8758 provides a simple interface between CVBS or Y/C analog signals and a digital colour decoder. Video inputs selection The input selector allows a choice from different video sources, and has one of the following configurations: A: Two Y/C and one CVBS signals B: One Y/C and two CVBS signals C: Three CVBS signals (only the Y channel is used). The wiring of the five video inputs (pins 2, 4, 6, 9 and 11) and the control of the two selection inputs (pins 5 and 12) will depend on the available video sources. * In configuration A, connect as follows: - Y1 to pin 11 - C1 to pin 4 - Y2 to pin 9 - C2 to pin 2 - CVBS3 to pin 6. Keep SEL2 (pin 5) LOW and select Y1/C1 or Y2/C2 by switching SEL1 (pin 12). CVBS3 is selected with SEL1 and SEL2 HIGH. * In configuration B, replace Y1 (or Y2) by a CVBS input (no more C1 or C2). The selection mode is the same. * In configuration C, connect as follows: - CVBS1 to pin 11 - CVBS2 to pin 9 - CVBS3 to pin 6. Use both SEL1 and SEL2 to select inputs. Remark: the video inputs selection is a static selection. Synchronization pulses
TDA8758
GATE A and GATE B pulses are synchronization pulses occurring during the sync period and rear porch respectively. They should be distinct. On the Y channel, the digital output of the ADC is compared to internal digital reference levels. The resultant outputs control the charge or discharge current of a capacitor connected to the CAGC pin. The voltage across this capacitor controls the gain of the video amplifier. This is the control loop. The sync level comparator is active during a positive-going pulse at the GATE A input. This means that sync pulse of the composite video signal is used as an amplitude reference. The bottom of the sync pulse is adjusted to obtain a digital output of logic 1 at the converter Y output. As the black level is digital level 64, the sync pulse will have a digital amplitude of 64 LSBs. The Peak White control loop is active when the selection pin PWE is LOW. Then, if the Y video signal exceeds the digital code of 255, it will be limited to avoid any over-range of the converter. The clamp level control is accomplished by using the same techniques as used for the gain control. On both Y and C channels, the black level digital comparators are active during a positive-going pulse at the GATE B input. On the Y channel, the clamping capacitor connected to the CCLPY pin will be charged or discharged to adjust the digital output to code 64. On the C channel, the clamping capacitor connected to the CCLPC pin will be charged or discharged to adjust the digital output to code 128.
1996 Feb 01
6
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCCA VCCD VCCO VCC PARAMETER analog supply voltage digital supply voltage output supply voltage supply voltage difference between VCCA and VCCD supply voltage difference between VCCO and VCCD supply voltage difference between VCCA and VCCO VI Vclk(p-p) IO Tstg Tamb Tj input voltage output current storage temperature operating ambient temperature junction temperature referenced to AGND AC input voltage for switching (peak-to-peak value) referenced to DGND CONDITIONS MIN. -0.3 -0.3 -0.3 -1.0 -1.0 -1.0 - - - -55 0 -
TDA8758
MAX. +7.0 +7.0 +7.0 +1.0 +1.0 +1.0 5.0 VCCO +6 +150 +70 +150 V V V V V V V V
UNIT
mA C C C
THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 72 UNIT K/W
CHARACTERISTICS VCCA = V10 to V3 = 4.75 to 5.25 V; VCCD = V21 to V18 = 4.75 to 5.25 V; VCCO1 = V41 to V43 = 4.75 to 5.25 V; VCC02 = V32 to V31 = 4.75 to 5.25 V; AGND and DGND shorted together; VCCA to VCCD = -0.25 to +0.25 V; VCCO to VCCD = -0.25 to +0.25 V; VCCA to VCCO = -0.25 to +0.25 V; Tamb = 0 to +70 C; typical values measured at VCCA = VCCD = VCCO = 5 V and Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VCCA VCCD VCCO ICCA ICCD ICCOtot analog supply voltage digital supply voltage output stages supply voltage analog supply current digital supply current total output supply current CL = 15 pF 4.75 4.75 4.75 - - - 5.0 5.0 5.0 59 28 19 5.25 5.25 5.25 70 40 28 V V V mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Video amplifier inputs Y1/CVBS1, Y2/CVBS2, CVBS3, CHROM1 AND CHROM2 INPUTS VI(p-p) input voltage (peak-to-peak value) Y channel C channel |Zi| CI 1996 Feb 01 input impedance input capacitance fi = 6 MHz fi = 6 MHz 7 AGC load with external capacitor; note 1 0.7 - - - - 1.0 25 2 1.4 - - - V V k pF
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - - 3.3 3.75 TYP.
TDA8758
MAX.
UNIT
SEL1 AND SEL2 TTL INPUTS; see Table 1 VIL VIH IIL IIH VIL VIH IIL IIH V13(min) V13(max) I12 V48 I48 V7 I7 ct B G Gstab LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current VI = 0.4 V VI = 2.7 V 0 2.0 -400 - 0 2.0 VI = 0.4 V VI = 2.7 V -400 - - - 0.8 VCCD - 20 V V A A V V A A V V
GATE A AND GATE B TTL INPUTS; see Figs 5 and 6 LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current AGC voltage for minimum gain at -3 dB AGC voltage for maximum gain at +3 dB AGC output current - 0.8 VCCD - 20 - -
AGC INPUT (PIN 13); see Fig.8
see Table 2 -
C-CHANNEL CLAMP INPUT (PIN 48) CLAMP voltage for code 128 output CLAMP output current - 3.45 V see Table 3 -
Y-CHANNEL CLAMP INPUT (PIN 7) CLAMP voltage for code 64 output CLAMP output current - - -3 fi = 4.43 MHz - - 3.70 V see Table 3 -63 15 - - - -55 - +3 0.5 6
Video amplifier dynamic characteristics crosstalk between video inputs (pins 2, 4, 6, 9 and 11) -3 dB bandwidth gain range gain stability as a function of: supply voltage supply voltage and temperature Analog-to-digital converter inputs CLK INPUT (PIN 42) VIL VIH IIL IIH CI LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current input capacitance Vclk = 0.4 V Vclk = 2.7 V fclk = 32 MHz 0 2.0 -400 - - - - - - 2 0.8 VCCD - 20 - V V A A pF % % VCCA = 4.75 to 5.25 V dB MHz dB
1996 Feb 01
8
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
SYMBOL PARAMETER CONDITIONS MIN. - - 1.15 -300 500 TYP.
TDA8758
MAX.
UNIT
OFY AND OFC INPUTS; 3-STATE; see Table 4 VIL VIH VI IIL IIH LOW level input voltage HIGH level input voltage input voltage in high impedance state LOW level input current HIGH level input current 0 2.6 - -370 - 0.2 VCCD - - 700 V V V A A
Analog-to-digital converter outputs ANOUTY AND ANOUTC OUTPUTS (PINS 16 AND 45); see Table 5 VANOUT VANOUT VANOUT(p-p) output voltage output voltage output voltage amplitude (peak-to-peak value) digital output = 00 digital output = 255 - - - 2.6 3.6 1.0 - - - V V V
DIGITAL OUTPUTS Y0 TO Y7, C0 TO C7 VOL VOH fclk(max) tCPH tCPL LOW level output voltage HIGH level output voltage IOL = 2 mA IOL = -0.4 mA note 2 0 2.4 - - 0.6 VCCD - - - 1.5 1.0 - - - - 3.0 V V
Switching characteristics; see Fig.9 CLK input maximum frequency clock pulse width HIGH clock pulse with LOW 30 12 12 - - fi = 4.43 MHz fi = 4.43 MHz note 3 fi = 4.43 MHz; note 4 V16,45 = 1.0 V (p-p); see Fig.4; PAL modulated ramp; note 5 see Fig.5; PAL modulated ramp; note 5 note 6 - - - - - 32 - - 0.75 0.4 1.5 0.5 -52 7.1 1.5 MHz ns ns
Analog signal processing from video input to digital output on both channels; 0 dB gain (fclk = 32 MHz) INL DNL AINL ADNL THD EB Gdiff DC integral non-linearity DC differential non-linearity AC integral non linearity AC differential non-linearity total harmonic distortion effective bits differential gain LSB LSB LSB LSB dB bits %
diff SVRR2
differential phase supply voltage ripple rejection
- -
0.6 -
1.5 5
deg %/V
1996 Feb 01
9
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8758
MAX.
UNIT
Timing (fclk = 32 MHz); see Fig.9 DIGITAL OUTPUTS (CL = 15 pF) tds th td tW tdZH tdZL tdHZ tdLZ Notes 1. 0 dB is obtained at the AGC amplifier when applying VI(p-p) = 1.0 V on Y channel. 2. It is recommended that the rise and fall times of the clock are 1 ns. In addition, a `good layout' for the digital and analog grounds is recommended. 3. THD (total harmonic distortion) is obtained with the addition of the first five harmonics: F THD = 20 log --------------------------------------------------------------------------------------------------------------2 2 2 2 2 (2nd) + (3rd) + (4th) + (5th) + (6th) a) F being the fundamental harmonic referenced at 0 dB for a full-scale sine wave input. 4. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8 K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB x 6.02 + 1.76 dB. 5. Measurement carried out using video analyser VM700A, where video analog signal is reconstructed through a digital-to-analog converter. 6. The supply voltage ripple rejection is the relative variation of the analog signal (full-scale signal at input) for 0.5 V of supply variation: ( V I ( 00 ) - V I ( FF ) ) x ( V I ( 00 ) - V I ( FF ) ) SVRR2 = ---------------------------------------------------------------------------------------------------V CCA sampling delay time output hold time output delay time clamp pulse width see Figs 6 and 7 - 10 - 2 - - - - 2 - 15 3 - - 18 - ns ns ns s
3-state output delay times; see Fig.10 enable HIGH enable LOW disable HIGH disable LOW 12 10 58 70 14 12 62 74 ns ns ns ns
1996 Feb 01
10
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
TDA8758
SEL2
handbook, full pagewidth
SEL2 2 4 6 Y CHANNEL 9 11 12 SEL1 SEL2 2 4 6 Y CHANNEL 9 11 12 SEL1
MGB471
CHROM2 CHROM1 CVBS3
2 4 6
5 CHROM2 C CHANNEL CHROM1 CVBS3
5 C CHANNEL
Y CHANNEL 9 11 12 SEL1
Y2/CVBS2 Y1/CVBS1
Y2/CVBS2 Y1/CVBS1
(a)
CHROM2 CHROM1 CVBS3
(b)
5 C CHANNEL
Y2/CVBS2 Y1/CVBS1
(c)
Fig.3 Video inputs selector.
Table 1 Video input selection SEL1 0 1 1 Note 1. X = don't care. SEL2 X(1) 0 1 Y-CHANNEL Y1/CVBS1 Y2/CVBS2 CVBS3 C-CHANNEL CHROM1 CHROM2 CHROM2 FIGURE 3 (a) (b) (c)
1996 Feb 01
11
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
Table 2 AGC output current PWE 0 0 GATE A 0 1 DIGITAL OUTPUT output < 255 output > 255 output < 0 0 < output < 255 output > 255 1 1 0 1 X(1) output < 0 0 < output < 255 Note 1. X = don't care. Table 3 CLAMP output current CLAMP C X(1) Y GATE B 1 0 1 DIGITAL OUTPUT output < 128 output > 128 X(1) output < 64 64 < output Note 1. X = don't care. Table 5 Output coding and ANOUTY (or ANOUTC) voltage (typical values) BINARY OUTPUTS STEP Underflow 0 1 . . 254 255 Overflow VI - 2.6 - - - - 3.6 - D7 0 0 0 . . 1 1 1 D6 0 0 0 . . 1 1 1 D5 0 0 0 . . 1 1 1 D4 0 0 0 . . 1 1 1 D3 0 0 0 . . 1 1 1 D2 0 0 0 . . 1 1 1 D1 0 0 0 . . 1 1 1 D0 0 0 1 . . 0 1 1 D7 1 1 1 . . 0 0 0 D6 0 0 0 . . 1 1 1 ICLAMP +54 A -54 A 0 A +54 A -54 A IAGC 0 A +540 A +8 A -8 A +540 A 0 A +8 A -8 A open Note 1. Use C 10 pF to DGND. Table 4 OFY and OFC input coding OFY (or OFC) 0 1 circuit(1)
TDA8758
Y0 to Y7 (or C0 TO C7) active, twos complement high impedance active, binary
TWOS COMPLIMENT D5 0 0 0 . . 1 1 1 D4 0 0 0 . . 1 1 1 D3 0 0 0 . . 1 1 1 D2 0 0 0 . . 1 1 1 D1 0 0 0 . . 1 1 1 D0 0 0 1 . . 0 1 1
1996 Feb 01
12
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
TDA8758
handbook, full pagewidth
MBE455
1.0 DIFFERENTIAL GAIN (%) 0.0
(1)
(2)
(4) (3)
(5)
1.0
(6)
2.0
3.0 1st 2nd 3rd 4th 5th step number 6th
(1) = 0.00; (2) = 0.09; (3) = -0.63; (4) = -0.45; (5) = -0.45; (6) = -1.23. Differential gain = max. (2) - min. (6) = 1.32%.
Fig.4 Typical differential gain result on VM700A.
handbook, full pagewidth
MBE456
2.0 DIFFERENTIAL PHASE (deg) 1.0
(1)
(2) (4) (3)
(5)
0
(6)
1.0
2.0 1st 2nd 3rd 4th 5th step number 6th
(1) = 0.00; (2) = 0.03; (3) = -0.53; (4) = -0.32; (5) = 0.01; (6) = -0.08. Differential phase = max. (2) - min. (3) = 0.56 deg.
Fig.5 Typical differential phase result on VM700A.
1996 Feb 01
13
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
TDA8758
handbook, full pagewidth digital
output level
255 peak-level gain control 213 standard picture level black-level clamping 64 sync-level control 0 tW GATE A
safety margin
time
MGB472
tW GATE B
Fig.6 Control mode Y channel.
andbook, full pagewidth digital
output level
255
black-level clamping 128 0 tW GATE B
MGB473
time
Fig.7 Control mode C-channel.
1996 Feb 01
14
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
TDA8758
handbook, full pagewidth AGC
8
MBE463
GAIN (dB)
6
4
2
0
2
4
6
8 3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9 4.0 C AGC voltage (V)
Dotted line: Typical curve (Tamb = 25 C; VCC = 5 V). Full line: Maximum envelope (Tamb = 0 to 70 C; VCC = 4.75 to 5.25 V).
Fig.8 AGC behaviour as a function temperature and supply voltage for ANOUTY output; fi = 4.43 MHz, Vi = 0 dB.
handbook, full pagewidth
t CPL t CPH CLK 1.4 V
sample N
sample N + 1
sample N + 2
Vl
t ds DATA C0 to C7 Y0 to Y7 DATA N-2 DATA N-1 td
th 2.4 V DATA N DATA N+1
MBE454
1.4 V 0.4 V
Fig.9 Timing diagram.
1996 Feb 01
15
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
TDA8758
handbook, full pagewidth
V CCD OFC OFY 50 % 1.15 V t dHZ HIGH 90 % output data t dLZ t dZL HIGH Z output data LOW 10 % TEST V CCD 3.3 k TDA8758 15 pF OFC OFY S1 t dLZ t dZL t dHZ t dZH S1 VCCD VCCD GND GND
MBE453
t dZH
50 % HIGH Z
50 %
fOFC = fOFY = 100 kHz.
Fig.10 Timing diagram and test conditions of 3-state output delay time.
1996 Feb 01
16
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
APPLICATION INFORMATION
TDA8758
AGND
handbook, full pagewidth
VCCA OGND1 3.3 nF REG1 44 43 42 CLK
OFC CCLPC 22 nF AGND 1 F 75 AGND 75 4.7 F CHROM1 SEL2 4.7 F 75 18 nF 22 nF AGND 75 4.7 F CVBS3 C CLPY SDN Y2/CVBS2 VCCA 4.7 F Y1/CVBS1 SEL1 48 1 2 3 4 5 6 18 nF 47
ANOUTC (1) 1 nF DEC2
V CCO1 ( 5 V) C0 C1 C2 C3
DEC1 CHROM2
46
45
41
40
39
38
37 36 35 34 33 32 31 C4 C5 C6 C7 VCCO2 ( 5 V) OGND2 Y0 Y1 Y2 Y3 Y4 Y5
TDA8758
7 8 9 10 11 12 13 14 470 nF PWE 15 16 17 18 19 20 21 VCCD ( 5 V) OFY 22 23 24 DEC3 1 nF ANOUTY AGND
(1)
30 29 28 27 26 25 REG2 3.3 nF GATE A Y7 Y6
75
CAGC
MGB476
DGND
GATE B
VCCA
(1) It is recommended that pin 16 and pin 45 are not loaded in order to avoid any distortion.
Fig.11 Application diagram.
1996 Feb 01
17
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
TDA8758
andbook, full pagewidth
U2
CHROMA IN 4.7 F C27 4 2 LUMA IN CVBS1 IN CVBS2 IN 4.7 F 4.7 F C11 4.7 F C25 IN0 IN1 GPSWO HSY HCL C12 C26 11 9 6 12 5 14 19 20 7 48 C14 8 1 C16 46 15 INADCY 16 45 CHR7 CHROMA1 CHROMA2 Y1/CVBS1 Y2/CVBS2 CVBS3 SEL1 SEL2 PWE GATE A GATE B CLMP_Y CLMP_C SDN DEC1 DEC2 DEC3 IN_ADC_Y IN_ADC_C AGC_CAP REG1 REG2 OE_Y OE_C OGND1 OGND2 DGND AGND 31 43 18 3 HSY HCL 48 1 HEADER 3 3SIP100 PAD100 TEST PT J10 HEADER 3 3SIP100 PAD100 TEST PT J9 INADCY INADCC VCC VCC VCC VCCA PAD100 J24 GROUND PAD100 J25 GROUND CX14 0.1 F CX5 0.1 F VCC 37 36 DEC_LLC DEC_REF LFCO RES VCCA 12 13 24 25 37 5 18 28 52 CX6 22 F VDDA VDD1 VDD2 VDD3 VDD4 29 26 27 4 36 3 HSY HCL LL27 CREF LFCO RES CX12 0.1 F XTAL1 IN0 IN1 VCCO1 VCCO2 VCCD VCCA 41 32 21 10 XTAL2 CX3 22 F VCCA CCX4 0.1 F CHR6 CHR5 CHR4 CHR3 CHR2 CHR1 CHR0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 33 34 35 36 37 38 39 40 23 24 25 26 27 28 29 30 CHR7 CHR6 CHR5 CHR4 CHR3 CHR2 CHR1 CHR0 CHR0 to 7 CVBS7 CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1 CVBS0 CVBS0 to 7 CHR7 CHR6 CHR5 CHR4 CHR3 CHR2 CHR1 CHR0 CVBS7 DEC_LLC CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1 CVBS0 13 12 11 10 9 8 7 6 23 22 21 20 17 16 15 14 44 33 34 24 25 26 27 10
9
1
61 60
SAA7151B
44 43
U4
CHR7 CHR6 CHR5 CHR4 CHR3 CHR2 CHR1 CHR0 CVBS7 CVBS6 CVBS5 CVBS4 CVBS3 CVBS2 CVBS1 CVBS0 SDAT XTAL
68LLC50
UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 D7 D6 D5 D4 D3 D2 D1 D0 HREF HS VS GTBS FSI 55 DEC_UV7 56 DEC_UV6 57 DEC_UV5 58 DEC_UV4 59 DEC_UV3 60 DEC_UV2 61 DEC_UV1 62 DEC_UV0 45 DEC_Y7 46 DEC_Y6 47 DEC_Y5 48 DEC_Y4 49 DEC_Y3 50 DEC_Y2 53 DEC_Y1 54 DEC_Y0 42 31 30 66 68 65 39 32 64 63 39 43 40 41 1 2 35 19 38 51 67 3 SDA SCL 4.7 k R64 DEC_FI DEC_RTC GPSWO DEC_HREF DEC_HS DEC_VS
DEC_UV0 to 7
0.1 F 0.1 F C13 0.022 F 0.022 F C15 0.022 F 0.022 F C17
TDA8758
CLK
42
220 R13 VCC
DEC_Y0 to 7
VCCA
INADCC 0.47 F C18 13 0.047 F 0.047 F C19
44
SAA7151B
XTAL1 GPSW1 GPSW2
C20 17 22
MUXC ODD RTCO FEIN GPSWO RSVRD IICSA SDA SCL SP AP VSSA VSS1 VSS2 VSS3 VSS4
VCC 1 1
VCC
47
JP14 2
3
JP15 2
3
TDA8758
VCC
2
1
JP5
HEADER 3 3SIP100
GND
U3
7 14 VCCA VCC 4.7 k CX7 0.1 F CX13 0.1 F R12 22 k R11 RES 11 19 2 1 12 5 8 17 LL1 to 5A LL3A LFCO LFCO2 CE MS RES VDDA VDDD VDDD LL1 to 5B LL3B LFCOSEL CLKREF PORD VSSA VSSD VSSD VSSD VSSD 10 20 16 15 3 4 6 9 13 18 C24 0.1 F 33 R15 33 R16 RES HEADER 4X2 8HH100 33 R14 1 3 JP16 5 7 2 4 6 8 DEC_LLC DEC_LLC2 DEC_CREF RES C21 10 pF XTAL2 Y2 24.576 MHz 2SIP100 XTAL1 C23 0.001 F L2 10 H
MBH012
SAA7197
C22 10 pF
20SOP300
Fig.12 Example of system application (DPC71 evaluation board).
1996 Feb 01
18
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
TDA8758
SOT313-2
c
y X
36 37
25 24 ZE
A
e
Q E HE A A2 A1 (A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 Q 0.69 0.59 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 93-06-15 94-12-19
1996 Feb 01
19
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices.
TDA8758
If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1996 Feb 01
20
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8758
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1996 Feb 01
21
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
NOTES
TDA8758
1996 Feb 01
22
Philips Semiconductors
Product specification
YC 8-bit low-power analog-to-digital video interface
NOTES
TDA8758
1996 Feb 01
23
Philips Semiconductors - a worldwide company
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Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-2724825 SCDS47 (c) Philips Electronics N.V. 1996
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1100/03/pp24 Document order number: Date of release: 1996 Feb 01 9397 750 00606

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